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1 ? fn8085.5 ISL1208 i 2 c ? real time clock/calendar low power rtc with battery backed sram the ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching and battery-backed user sram. the oscillator uses an external, low-cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. pinout ISL1208 (8 ld msop, soic) top view features ? real time clock/calendar - tracks time in hours, minutes, and seconds - day of the week, day, month, and year ? 15 selectable frequency outputs ? single alarm - settable to the second, minute, hour, day of the week, day, or month - single event or pulse interrupt mode ? automatic backup to battery or super cap ? power failure detection ? on-chip oscillator compensation ? 2 bytes battery-backed user sram ?i 2 c interface - 400khz data transfer rate ? 400na battery supply current ? same pin out as st m41t xx and maxim ds13xx devices ? small package options - 8 ld msop and soic packages ? pb-free plus anneal available (rohs compliant) applications ? utility meters ? hvac equipment ? audio/video components ? set top box/television ? modems ? network routers, hubs, switches, bridges ? cellular infrastructure equipment ? fixed broadband wireless equipment ? pagers/pda ? pos equipment ? test meters/fixtures ? office automation (copiers, fax) ? home appliances ? computer products ? other industrial/medical/automotive ordering information part number part marking v dd range temp. range (c) package ISL1208iu8 ags 2.7v to 5.5v -40 to +85 8 ld msop ISL1208iu8-tk ags 2.7v to 5.5v -40 to +85 8 ld msop tape & reel ISL1208iu8z (note) anw 2.7v to 5.5v -40 to +85 8 ld msop (pb-free) ISL1208iu8z-tk (note) anw 2.7v to 5.5v -40 to +85 8 ld msop tape & reel (pb-free) ISL1208ib8 1208i 2.7v to 5.5v -40 to +85 8 ld soic ISL1208ib8-tk 1208i 2.7v to 5.5v -40 to +85 8 ld soic tape & reel ISL1208ib8z (note) 1208zi 2.7v to 5.5v -40 to +85 8 ld soic (pb-free) ISL1208ib8z-tk (note) 1208zi 2.7v to 5.5v -40 to +85 8 ld soic tape & reel (pb-free) note: intersil pb-free plus anneal produc ts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. * contact factory for availability. 1 2 3 4 8 7 x1 x2 v bat v dd irq /f out scl sda gnd 5 6 data sheet august 23, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2004-2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn8085.5 august 23, 2006 block diagram i 2 c interface rtc control logic alarm frequency out rtc divider sda buffer crystal oscillator por switch scl buffer sda scl x1 x2 v dd v bat irq / f out internal supply v trip seconds minutes hours day of week date month year user sram control registers pin descriptions pin number symbol description 1 x1 the x1 pin is the input of an inverting amplifier and is in tended to be connected to one pin of an external 32.768khz quartz crystal. x1 can also be driven directly from a 32.768khz source. 2 x2 the x2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768khz quart z crystal. 3v bat this input provides a backup s upply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin should be tied to ground if not used. 4 gnd ground. 5 sda serial data (sda) is a bidirectiona l pin used to transfer serial data into and out of the device. it has an open drain outp ut and may be wire or?ed with other open drain or open collector outputs. 6 scl the serial clock (scl) input is used to cl ock all serial data into and out of the device. 7irq /f ou t interrupt output/frequency output is a multi-functional pin that can be used as interrupt or frequency output pin. the function is set via the configuration register. 8v dd power supply. ISL1208
3 fn8085.5 august 23, 2006 absolute m aximum ratings voltage on v dd , v bat , scl, sda, and irq pins (respect to ground) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7.0v voltage on x1 and x2 pins (respect to ground) . . . . . . . . . . . .-0.5v to v dd + 0.5 (v dd mode) -0.5v to v bat + 0.5 (v bat mode) storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. dc operating characteristics ? rtc temperature = -40c to +85c, unless otherwise stated. symbol parameter conditions min typ (note 4) max units notes v dd main power supply 2.7 5.5 v v bat battery supply voltage 1.8 5.5 v i dd1 supply current v dd = 5v 2 6 a 1, 2 v dd = 3v 1.2 4 a i dd2 supply current with i 2 c active v dd = 5v 40 120 a 1, 2 i dd3 supply current (low power mode) v dd = 5v, lpmode = 1 1.4 5 a 1 i bat battery supply current v bat = 3v 400 950 na 1 i li input leakage current on scl 100 na i lo i/o leakage current on sda 100 na v trip v bat mode threshold 1.6 2.2 2.6 v v triphys v trip hysteresis 10 30 75 mv v bathys v bat hysteresis 15 50 100 mv irq /f out v ol output low voltage v dd = 5v i ol = 3ma 0.4 v v dd = 2.7v i ol = 1ma 0.4 v power-down timing temperature = -40c to +85c, unless otherwise stated. symbol parameter conditions min typ (note 4) max units notes v dd sr- v dd negative slewrate 10 v/ms 3 serial interface specifications over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min typ (note 4) max units notes serial interface specs v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v v ol sda output buffer low voltage, sinking 3ma 00.4v ISL1208
4 fn8085.5 august 23, 2006 cpin sda and scl pin capacitance t a = 25c, f = 1mhz, v dd = 5v, v in =0v, v out = 0v 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window. 20 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0ns t r sda and scl rise time from 30% to 70% of v dd 20 + 0.1 x cb 300 ns t f sda and scl fall time from 70% to 30% of v dd 20 + 0.1 x cb 300 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2~2.5k ? . for cb = 40pf, max is about 15~20k ? 1k ? notes: 1. irq & f out inactive. 2. lpmode = 0 (default). 3. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 4. typical values are for t = 25c and 3.3v supply voltage. serial interface specifications over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min typ (note 4) max units notes ISL1208
5 fn8085.5 august 23, 2006 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ISL1208
6 fn8085.5 august 23, 2006 typical performance curves temperature is 25c unless otherwise specified figure 1. i bat vs v bat figure 2. i bat vs temperature at v bat = 3v figure 3. i dd1 vs temperature figure 4. i dd1 vs v cc with lpmode on & off figure 5. i dd1 vs f out at v dd = 3.3v figure 6. i dd1 vs f out at v dd = 5v 000e+0 100e-9 200e-9 300e-9 400e-9 500e-9 600e-9 700e-9 800e-9 900e-9 1e-6 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v bat (v) i bat (a) 000e+0 200e-9 400e-9 600e-9 800e-9 1e-6 -40-200 20406080 temperature (c) i bat (a) 1.0e-06 1.2e-06 1.4e-06 1.6e-06 1.8e-06 2.0e-06 2.2e-06 2.4e-06 -40-200 20406080 temperature (c) i dd1 (a) v cc = 5v v cc = 3.3v 400.0e-9 600.0e-9 800.0e-9 1.0e-6 1.2e-6 1.4e-6 1.6e-6 1.8e-6 2.0e-6 2.2e-6 2.4e-6 2.53.03.54.04.55.05.5 v cc (v) lpmode = 0 lpmode = 1 i dd1 (a) 1.2e-6 1.3e-6 1.4e-6 1.5e-6 1.6e-6 1.7e-6 1.8e-6 1.9e-6 2.0e-6 2.1e-6 f out (hz) 1/8 2 8 32 1024 32768 1/2 1/32 1/16 1/4 1 4 16 64 4096 i dd1 (a) 1.8e-6 1.9e-6 2.0e-6 2.1e-6 2.2e-6 2.3e-6 2.4e-6 2.5e-6 2.6e-6 2.7e-6 2.8e-6 2.9e-6 3.0e-6 f out (hz) 1/8 2 8 32 1024 32768 1/2 1/32 1/16 1/4 1 4 16 64 4096 i dd1 (a) ISL1208
7 fn8085.5 august 23, 2006 general description the ISL1208 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, periodic or polled alarm, intelligent battery backup switching, and battery-backed user sram. the oscillator uses an external, low-cost 32.768khz crystal. the real time clock tracks time with separate registers for hours, minutes, and seconds. the device has calendar registers for date, month, ye ar and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. the ISL1208's powerful alarm can be set to any clock/calendar value for a match. for example, every minute, every tuesday or at 5:23 am on march 21. the alarm status is available by checking the status register, or the device can be configured to provide a hardware interrupt via the irq pin. there is a repeat mode for the alarm allowing a periodic interrupt ev ery minute, every hour, every day, etc. the device also offers a backup power input pin. this v bat pin allows the device to be backed up by battery or supercap with automatic switchover from v dd to v bat . the entire ISL1208 device is fully oper ational from 2.0v to 5.5v and the clock/calendar portion of the device remains fully operational down to 1.8v (standby mode). pin description x1, x2 the x1 and x2 pins are the i nput and output, respectively, of an inverting amplifier. an external 32.768khz quartz crystal is used with the ISL1208 to supply a timebase for the real time clock. internal compensation circuitry provides high accuracy over the operating temperature range from -40c to +85c. this oscillator compensation network can be used to calibrate the crystal timing accuracy over temperature either during manufacturing or with an external temperature sensor and mi crocontroller for active compensation. the device can also be driven directly from a 32.768khz source at pin x1. v bat this input provides a backup supply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin can be connected to a battery, a super cap or tied to ground if not used. irq /f out (interrupt output/frequency output) this dual function pin can be used as an interrupt or frequency output pin. the irq /f out mode is selected via the frequency out control bits of the control/status register. ? interrupt mode. the pin provides an interrupt signal output. this signal notifies a host processor that an alarm has occurred and requests action. it is an open drain active low output. ? frequency output mode. the pin outputs a clock signal which is related to the crystal frequency. the frequency output is user selectable and enabled via the i 2 c bus. it is an open drain active low output. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gated). it is disabled when the backup power supply on the v bat pin is activated to minimize power consumption. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be ored with other open drain or open collector outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires the use of a pull-up resistor. the output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. the circuit is designed for 400khz i 2 c interface speeds. it is disabled when the backup power supply on the v bat pin is activated. v dd , gnd chip power supply and ground pins. the device will operate with a power supply from 2.0v to 5.5vdc. a 0.1f capacitor is recommended on the v dd pin to ground. functional description power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power figure 7. standard output load for testing the device with v dd = 5.0v sda and irq /fout 1533 ? 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circuit for v dd = 5v figure 8. recommended crystal connection x1 x2 ISL1208
8 fn8085.5 august 23, 2006 the ISL1208 for up to 10 years. another option is to use a super cap for applications where v dd is interrupted for up to a month. see the applications section for more information. normal mode (v dd ) to battery backup mode (v bat ) to transition from the v dd to v bat mode, both of the following conditions must be met: condition 1: v dd < v bat - v bathys where v bathys 50mv condition 2: v dd < v trip where v trip 2.2v battery backup mode (v bat ) to normal mode (v dd ) the ISL1208 device will switch from the v bat to v dd mode when one of the following conditions occurs: condition 1: v dd > v bat + v bathys where v bathys 50mv condition 2: v dd > v trip + v triphys where v triphys 30mv these power control situations are illustrated in figures 9 and 10. the i 2 c bus is deactivated in battery backup mode to provide lower power. aside from th is, all rtc functions are operational during battery backup mode. except for scl and sda, all the inputs and outputs of the ISL1208 are active during battery backup mode unless disabled via the control register. the user sram is operational in battery backup mode down to 2v. power failure detection the ISL1208 provides a real time clock failure bit (rtcf) to detect total power failure. it allows users to determine if the device has powered up after having lost all power to the device (both v dd and v bat ). low power mode the normal power switching of the ISL1208 is designed to switch into battery backup mode only if the v dd power is lost. this will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. another mode, called low power mode, is available to allow direct switching from v dd to v bat without requiring v dd to drop below v trip . since the additional monitoring of v dd vs v trip is no longer needed, that circuitry is shut down and less power is used while operating from v dd . power savings are typically 600na at v dd = 5v. low power mode is activated via the lpmode bit in the control and status registers. low power mode is useful in systems where v dd is normally higher than v bat at all times. the device will switch from v dd to v bat when v dd drops below v bat , with about 50mv of hysteresis to prev ent any swit chback of v dd after switchover. in a system with a v dd = 5v and backup lithium battery of v bat = 3v, low power mode can be used. however, it is not recommended to use low power mode in a system with v dd = 3.3v 10%, v bat 3.0v, and when there is a finite i-r voltage drop in the v dd line. interseal? battery saver the ISL1208 has the interseal? battery saver which prevents initial battery current drain before it is first used. for example, battery-backed rtcs are commonly packaged on a board with a battery connected. in order to preserve battery life, the ISL1208 will no t draw any power from the battery source until after the device is first powered up from the v dd source. thereafter, the device will switchover to battery backup mode whenever v dd power is lost. real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of second, minute, hour, day of week, date, mont h, and year. the rtc also has leap-year correction. the clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or am /pm format. when the ISL1208 powers up after the loss of both v dd and v bat , the clock will v bat - v bathys v bat v bat + v bathys battery backup mode v dd v trip 2.2v 1.8v figure 9. battery switchover when v bat < v trip figure 10. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery backup mode v dd v trip 3.0v 2.2v ISL1208
9 fn8085.5 august 23, 2006 not begin incrementing until at least one byte is written to the clock register. accuracy of the real time clock the accuracy of the real time clock depends on the frequency of the quartz crystal that is used as the time base for the rtc. since the resonant frequency of a crystal is temperature dependent, the rtc performance will also be dependent upon temperature. the frequency deviation of the crystal is a function of th e turnover temperature of the crystal from the crystal?s nominal frequency. for example, a ~20ppm frequency deviation translates into an accuracy of ~1 minute per month. these parameters are available from the crystal manufacturer. the ISL1208 provides on-chip crystal compensation networks to adjust load capacitance to tune oscillator frequency from -94ppm to +140ppm. for more detailed information see the application section. single event and interrupt the alarm mode is enabled via the alme bit. choosing single event or interrupt alarm mode is selected via the im bit. note that when the frequ ency output function is enabled, the alarm function is disabled. the standard alarm allows for alarms of time, date, day of the week, month, and year. when a time alarm occurs in single event mode, an irq pin will be pulled low and the alarm status bit (alm) will be set to ?1?. the pulsed interrupt mode allows for repetitive or recurring alarm functionality. hence, once the alarm is set, the device will continue to alarm for each occurring match of the alarm and present time. thus, it will alarm as often as every minute (if only the nth second is set) or as infrequently as once a year (if at least the nth month is set). during pulsed interrupt mode, the irq pin will be pulled low for 250ms and the alarm status bit (alm) will be set to ?1?. note: the alm bit can be reset by the user or cleared automatically using the auto reset mode (see arst bit). the alarm function can be enabled/disabled during battery backup mode using the fobatb bit. for more information on the alarm, please see the alarm registers description. frequency output mode the ISL1208 has the option to provide a frequency output signal using the irq /f out pin. the frequency output mode is set by using the fo bits to select 15 possible output frequency values from 0 to 32khz. the frequency output can be enabled/disabled during battery backup mode using the fobatb bit. general purpose user sram the ISL1208 provides 2 bytes of user sram. the sram will continue to operate in batt ery backup mode. however, it should be noted that the i 2 c bus is disabled in battery backup mode. i 2 c serial interface the ISL1208 has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compatible with other industry i 2 c serial bus protocols using a bidirectional data signal (sda) and a clock signal (scl). oscillator compensation the ISL1208 provides the option of timing correction due to temperature variation of the crystal oscillator for either manufacturing calibration or active calibration. the total possible compensation is typically -94ppm to +140ppm. two compensation mechanisms that are available are as follows: 1. an analog trimming (atr) regi ster that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. the individual digital capacitor is selectable from a range of 9pf to 40.5pf (based upon 32.758khz). this translates to a calculated compensation of approximately -34ppm to +80ppm. (see atr description.) 2. a digital trimming register (dtr) that can be used to adjust the timing counter by 60ppm. (see dtr description.) also provided is the ability to adjust the crystal capacitance when the ISL1208 switches from v dd to battery backup mode. (see battery mode atr selection for more details.) register descriptions the battery-backed registers are accessible following a slave byte of ?1101111x? and reads or writes to addresses [00h:13h]. the defin ed addresses and default values are described in the table 1. address 09h is not used. reads or writes to 09h will not affect operation of the device but should be avoided. register access the contents of the registers can be modified by performing a byte or a page write operati on directly to any register address. the registers are divided into 4 sections. these are: 1. real time clock (7 bytes): address 00h to 06h. 2. control and status (5 bytes): address 07h to 0bh. 3. alarm (6 bytes): address 0ch to 11h. 4. user sram (2 bytes): address 12h to 13h. there are no addresses above 13h. ISL1208
10 fn8085.5 august 23, 2006 write capability is allowable into the rtc registers (00h to 06h) only when the wrtc bit (bit 4 of address 07h) is set to ?1?. a multi-byte read or write operation is limited to one section per operation. access to another section requires a new operation. a read or write can begin at any address within the section. a register can be read by performing a random read at any address at any time. this returns the contents of that register location. additional registers are read by performing a sequential read. for the rtc and alarm registers, the read instruction latches all clock r egisters into a buffer, so an update of the clock does not change the time being read. a sequential read will not result in the output of data from the memory array. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read, the address remains at t he previous address +1 so the user can execute a current address read and continue reading the next register. it is not necessary to set the wrtc bit prior to writing into the control and status, alarm, and user sram registers. table 1. register memory map addr. section reg name bit range default 76543210 00h rtc sc 0 sc22 sc21 sc20 sc13 sc12 sc11 sc10 0-59 00h 01h mn 0 mn22 mn21 mn20 mn13 mn12 mn11 mn10 0-59 00h 02h hr mil 0 hr21 hr20 hr13 hr12 hr11 hr10 0-23 00h 03h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1-31 00h 04h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1-12 00h 05h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0-99 00h 06h dw00000dw2dw1dw00-600h 07h control and status sr arst xtoscb reserved wrtc reserved alm bat rtcf n/a 01h 08h int im alme lpmode fobatb fo3 fo2 fo1 fo0 n/a 00h 09h reserved n/a 00h 0ah atr bmatr1 bmatr0 atr5 atr4 atr3 atr2 atr1 atr0 n/a 00h 0bh dtr reserved dtr2 dtr1 dtr0 n/a 00h 0ch alarm sca esca asc22 asc21 asc20 asc13 asc12 asc11 asc10 00-59 00h 0dh mna emna amn22 amn21 amn20 amn13 amn12 amn11 amn10 00-59 00h 0eh hra ehra 0 ahr21 ahr20 ahr13 ahr12 ahr11 ahr10 0-23 00h 0fh dta edta 0 adt21 adt20 adt13 adt12 adt11 adt10 1-31 00h 10h moa emoa 0 0 amo20 amo13 amo12 amo11 amo10 1-12 00h 11h dwaedwa0000adw12adw11adw100-600h 12h user usr1 usr17 usr16 usr15 usr14 usr13 usr12 usr11 usr10 n/a 00h 13h usr2 usr27 usr26 usr25 usr24 usr23 usr22 usr21 usr20 n/a 00h ISL1208
11 fn8085.5 august 23, 2006 real time clock registers addresses [00h to 06h] rtc registers (sc, mn, hr, dt, mo, yr, dw) these registers depict bcd repr esentations of the time. as such, sc (seconds) and mn (minutes) range from 0 to 59, hr (hour) can either be a 12-hour or 24-hour mode, dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99, and dw (day of the week) is 0 to 6. the dw register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1- 2-? the assignment of a numeri cal value to a specific day of the week is arbitrary a nd may be decided by the system software designer. the default value is defined as ?0?. 24 hour time if the mil bit of the hr register is ?1?, the rtc uses a 24- hour format. if the mil bit is ?0?, the rtc uses a 12-hour format and hr21 bit functions as an am/pm indicator with a ?1? representing pm. the clock defaults to 12-hour format time with hr21 = ?0?. leap years leap years add the day february 29 and are defined as those years that are divisible by 4. ye ars divisible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year, the year 2100 is not. the ISL1208 does not correct for the leap year in the year 2100. control and status registers addresses [07h to 0bh] the control and status regist ers consist of the status register, interrupt and alarm register, analog trimming and digital trimming registers. status register (sr) the status register is located in the memory map at address 07h. this is a volatile register that provides either control or status of rtc failur e, battery mode, alarm trigger, write protection of clock counte r, crystal oscillator enable and auto reset of status bits. real time clock fail bit (rtcf) this bit is set to a ?1? after a total power failure. this is a read only bit that is set by hardwa re (ISL1208 internally) when the device powers up after having lost all power to the device (both v dd and v bat go to 0v). the bit is set regardless of whether v dd or v bat is applied first. the loss of only one of the supplies does not set the rtcf bit to ?1?. on power-up after a total power failure, all registers are set to their default states and the clock will not increment until at least one byte is written to the clock register. the first valid write to the rtc section after a complete power failure resets the rtcf bit to ?0? (writing one byte is sufficient). battery bit (bat) this bit is set to a ?1? when the device enters battery backup mode. this bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to ?0?, not ?1?. alarm bit (alm) these bits announce if the alarm matches the real time clock. if there is a match, the re spective bit is set to ?1?. this bit can be manually reset to ?0? by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to ?0?, not ?1?. note: an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read operation is complete. write rtc enable bit (wrtc) the wrtc bit enables or disables write capability into the rtc timing registers. the factory default setting of this bit is ?0?. upon initialization or power-up, the wrtc must be set to ?1? to enable the rtc. upon the completion of a valid write (stop), the rtc starts counting. the rtc internal 1hz signal is synchronized to the stop condition during a valid write cycle. crystal oscillator enable bit (xtoscb) this bit enables/disables the internal crystal oscillator. when the xtoscb is set to ?1?, the oscillator is disabled, and the x1 pin allows for an external 32khz signal to drive the rtc. the xtoscb bit is set to ?0? on powerup. auto reset enable bit (arst) this bit enables/disables the aut omatic reset of the bat and alm status bits only. when ar st bit is set to ?1?, these status bits are reset to ?0? after a valid read of the respective status register (with a valid stop condition). when the arst is cleared to ?0?, the user must manually reset the bat and alm bits. interrupt control register (int) table 2. status register (sr) addr 7 6 5 4 3 2 1 0 07h arst xtoscb reserved wrtc reserved alm bat rtcf default00 000000 table 3. interrupt control register (int) addr7 6 5 4 3210 08h im alme lpmode fobatb fo3 fo2 fo1 fo0 default0 0 0 0 0000 ISL1208
12 fn8085.5 august 23, 2006 frequency out control bits (fo <3:0>) these bits enable/disable the frequency output function and select the output frequency at the irq /f out pin. see table 4 for frequency selection. when the frequency mode is enabled, it will override the alarm mode at the irq /f out pin. frequency output and interrupt bit (fobatb) this bit enables/disables the f out /irq pin during battery backup mode (i.e. v bat power source active). when the fobatb is set to ?1? the f out /irq pin is disabled during battery backup mode. this means that both the frequency output and alarm output func tions are disabled. when the fobatb is cleared to ?0?, the f out /irq pin is enabled during battery backup mode. low power mode bit (lpmode) this bit enables/disables low power mode. with lpmode = ?0?, the device will be in normal mode and the v bat supply will be used when v dd < v bat - v bathys and v dd < v trip . with lpmode = ?1?, the device will be in low power mode and the v bat supply will be used when v dd < v bat -v bathys . there is a supply current saving of about 600na when using lpmode = ?1? with v dd = 5v. (see typical performance curves: i dd vs v cc with lpmode on & off.) alarm enable bit (alme) this bit enables/disables the alarm function. when the alme bit is set to ?1?, the alarm function is enabled. when the alme is cleared to ?0?, the alarm function is disabled. the alarm function can operate in either a single event alarm or a periodic interrupt alarm (see im bit). note: when the frequency output mode is enabled, the alarm function is disabled. interrupt/alarm mode bit (im) this bit enables/disables the interrupt mode of the alarm function. when the im bit is set to ?1?, the alarm will operate in the interrupt mode, where an active low pulse width of 250ms will appear at the irq /f out pin when the rtc is triggered by the alarm as defined by the alarm registers (0ch to 11h). when the im bit is cleared to ?0?, the alarm will operate in standard mode, where the irq /f out pin will be tied low until the alm status bit is cleared to ?0?. analog trimming register analog trimming register (atr<5:0>) six analog trimming bits, atr0 to atr5 , are provided in order to adjust the on-chip load capacitance value for frequency compensation of the rtc. each bit has a different weight for capacitance adjust ment. for example, using a citizen cfs-206 crystal with di fferent atr bit combinations provides an estimated ppm adjustment range from -34 to +80ppm to the nominal frequency compensation. the combination of analog and digital trimming can give up to -94 to +140ppm of total adjustment. the effective on-chip series load capacitance, c load , ranges from 4.5pf to 20.25pf with a mid-scale value of 12.5pf (default). c load is changed via two digitally controlled capacitors, c x1 and c x2 , connected from the x1 table 4. frequency selection of f out pin frequency, f out units fo3 fo2 fo1 fo0 0 hz0 000 32768 hz 0 0 0 1 4096 hz 0 0 1 0 1024 hz 0 0 1 1 64 hz0 100 32 hz0 101 16 hz0 110 8 hz0 111 4 hz1 000 2 hz1 001 1 hz1 010 1/2 hz1 011 1/4 hz1 100 1/8 hz1 101 1/16 hz 1 1 1 0 1/32 hz 1 1 1 1 im bit interrupt/alarm frequency 0 single time event set by alarm 1 repetitive/recurring time event set by alarm figure 11. diagram of atr c x1 x1 x2 crystal oscillator c x2 ISL1208
13 fn8085.5 august 23, 2006 and x2 pins to ground (see figure 11). the value of c x1 and c x2 is given by the following formula: the effective series load capacitance is the combination of c x1 and c x2 : for example, c load (atr=00000) = 12.5pf, c load (atr=100000) = 4.5pf, and c load (atr=011111) = 20.25pf. the entire range for the series combination of load capacitance goes from 4.5pf to 20.25pf in 0.25pf steps. note that these are typical values. battery mode atr selection (bmatr <1:0>) since the accuracy of the crystal oscillator is dependent on the v dd /v bat operation, the ISL1208 provides the capability to adjust the capacitance between v dd and v bat when the device switches between power sources. digital trimming register (dtr <2:0>) the digital trimming bits dtr0, dtr1, and dtr2 adjust the average number of counts per second and average the ppm error to achieve better accuracy. ? dtr2 is a sign bit. dtr2 = ?0? means frequency compensation is >0. dtr2 = ?1? means frequency compensation is <0. ? dtr1 and dtr0 are both scale bits. dtr1 gives 40ppm adjustment and dtr0 gives 20ppm adjustment. a range from -60ppm to +60ppm can be represented by using these three bits (see table 5). alarm registers addresses [0ch to 11h] the alarm register bytes are set up identical to the rtc register bytes, except that the msb of each byte functions as an enable bit (enable = ?1?). these enable bits specify which alarm registers (seconds, minutes, etc) are used to make the comparison. note that there is no alarm byte for year. the alarm function works as a comparison between the alarm registers and the rtc registers. as the rtc advances, the alarm will be triggered once a match occurs between the alarm registers an d the rtc registers. any one alarm register, multiple registers, or all registers can be enabled for a match. there are two alarm operation modes: single event and periodic interrupt mode: ? single event mode is enabled by setting the alme bit to ?1?, the im bit to ?0?, and disabling the frequency output. this mode permits a one-time match between the alarm registers and the rtc registers. once this match occurs, the alm bit is set to ?1? and the irq output will be pulled low and will remain low until the alm bit is reset. this can be done manually or by us ing the auto-reset feature. ? interrupt mode is enabled by setting the alme bit to ?1?, the im bit to ?1?, and dis abling the frequency output. the irq output will now be pulsed each time an alarm occurs. this means that once the inte rrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. this mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. to clear an alarm, the alm bit in the status register must be set to ?0? with a write. note that if the arst bit is set to 1 (address 07h, bit 7), the alm bit will automatically be cleared when the status register is read. bmatr1 bmatr0 delta capacitance (c bat to c vdd ) 0 0 0pf 0 1 -0.5pf ( +2ppm) 1 0 +0.5pf ( -2ppm) 1 1 +1pf ( -4ppm) c x 16 b5 ? 8b4 4b3 2b2 1b1 0.5b0 9 + ? + ? + ? + ? + ? + () pf = c load 1 1 c x1 ---------- - 1 c x2 ---------- - + ?? ?? ---------------------------------- - = c load 16 b5 ? 8 b4 4 b3 2 b2 1 b1 0.5 b0 9 + ? + ? + ? + ? + ? + 2 ----------------------------------------------------------------------------------------------------------------------------- ?? ?? pf = table 5. digital trimming registers dtr register estimated frequency ppm dtr2 dtr1 dtr0 0 0 0 0 (default) 001 +20 010 +40 011 +60 100 0 101 -20 110 -40 111 -60 ISL1208
14 fn8085.5 august 23, 2006 below are examples of both single event and periodic interrupt mode alarms. example 1 ? alarm set with single interrupt (im=?0?) a single alarm will occur on january 1 at 11:30am. a. set alarm regi sters as follows: b. also the alme bit mu st be set as follows: xx indicate othe r control bits after these registers are set, an alarm will be generated when the rtc advances to exactly 11:30am on january 1 (after seconds changes from 59 to 00) by setting the alm bit in the status register to ?1? and also bringing the irq output low. example 2 ? pulsed interrupt once per minute (im=?1?) interrupts at one minute intervals when the seconds register is at 30 seconds. a. set alarm regi sters as follows: b. set the interrupt register as follows: xx indicate othe r control bits once the registers are set, the following waveform will be seen at irq-: note that the status register alm bit will be set each time the alarm is triggered, but does not need to be read or cleared. user registers addresses [12h to 13h] these registers are 2 bytes of battery-backed user memory storage. i 2 c serial interface the ISL1208 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operat ions. therefore, the ISL1208 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 12). on power-up of the ISL1208, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the ISL1208 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 12). a start condition is ignored during the power- up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 12). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the alarm register bit description 76543210hex sca 00000000 00hsec onds disabled mna 10110000 b0hminutes set to 30, enabled hra 10010001 91hhours set to 11, enabled dta 10000001 81hdate set to 1, enabled moa 10000001 81hmonth set to 1, enabled dwa 00000000 00hday of week disabled control register bit description 76543210hex int 01xx0000 x0he nable alarm alarm register bit description 76543210hex sca 10110000b0hseconds set to 30, enabled mna 00000000 00hminutes disabled hra 00000000 00hhours disabled dta 00000000 00hdate disabled moa 00000000 00hmonth disabled dwa 00000000 00hday of week disabled control register bit description 76543210hex int 11xx0000 x0he nable alarm and int mode 60 sec rtc and alarm registers are both ?30? sec ISL1208
15 fn8085.5 august 23, 2006 receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 13). the ISL1208 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful receipt of an address byte. the ISL1208 also responds with an ack after receiving a data byte of a write operation. th e master must respond with an ack after receiving a data byte of a read operation. figure 12. valid data changes, start, and stop conditions figure 13. acknowledge response from receiver figure 14. byte write sequence sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte data byte a c k signals from the master signals from the ISL1208 a c k 10 0 11 a c k write signal at sda 0000 111 address byte ISL1208
16 fn8085.5 august 23, 2006 device addressing following a start condition, the master must output a slave address byte. the 7 msbs are the device identifier. these bits are ?1101111?. slave bits ?1101? access the register. slave bits ?111? specify the device select bits. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, then a read operation is selected. a ?0? selects a write operation (refer to figure 15). after loading the entire slave address byte from the sda bus, the ISL1208 compares the device identifier and device select bits with ?1101111?. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up the internal address counter is set to addr ess 0h, so a current address read of the ccr array starts at address 0h. when required, as part of a random read, the master must supply the 1 word address bytes as shown in figure 16. in a random read operation, t he slave byte in the ?dummy write? portion must match t he slave byte in the ?read? section. for a random read of the clock/control registers, the slave byte must be ?1101111x? in both places. write operation a write operation requires a star t condition, followed by a valid identification byte, a valid address byte, a data byte, and a stop condition. after each of the three bytes, the ISL1208 responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a three byte instruction followed by one or more data bytes (see figure 16). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the ISL1208 re sponds with an ack. then the ISL1208 transmits data by tes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condit ion) following the last bit of the last data byte (see figure 16). the data bytes are from the memory location indicated by an internal pointer. this pointer initial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. after reaching the memory location 13h the pointer ?rolls over? to 00h, and the device continues to output data for each ack received. figure 15. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 1 1 1 r/w 1 word address figure 16. read sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w =0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1111 10 1 11 11 ISL1208
17 fn8085.5 august 23, 2006 application section oscillator crys tal requirements the ISL1208 uses a standard 32.768khz crystal. either through hole or surface mount crystals can be used. table 6 lists some recommended surface mount crystals and the parameters of each. this list is not exhaustive and other surface mount devices can be used with the ISL1208 if their specifications are very similar to the devices listed. the crystal should have a required parallel load capacitance of 12.5pf and an equivalent series resistance of less than 50k. the crystal?s temperature range specification should match the application. many crystals are rated for -10c to +60c (especially through hole and tuning fork types), so an appropriate crystal should be selected if extended temperature range is required. crystal oscillator frequency adjustment the ISL1208 device contains circuitry for adjusting the frequency of the crystal oscillator. this circuitry can be used to trim oscillator initial accuracy as well as adjust the frequency to compensate for temperature changes. the analog trimming register (atr) is used to adjust the load capacitance seen by the crystal. there are six bits of atr control, with linear capacitance increments available for adjustment. since the atr adjust ment is essentially ?pulling? the frequency of the oscillator, the resulting frequency changes will not be linear with incremental capacitance changes. the equations whic h govern pulling show that lower capacitor values of atr adjustment will provide larger increments. also, the higher values of atr adjustment will produce smaller incremental frequency changes. these values typically vary from 6-10 ppm/bit at the low end to <1ppm/bit at the highest capacitance settings. the range afforded by the atr adjustment with a typical surface mount crystal is typically -34 to +80ppm around the atr=0 default setting because of this property. the user should note this when using the atr for calibration. the temperature drift of the capacitance used in the atr control is extremely low, so this feature can be used for temperature compensation with good accuracy. in addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the ISL1208. there are 3 bits known as the digital trimming register (dtr). the range provided is 60ppm in increments of 20ppm. dtr operates by adding or skipping pulses in the clock counter. it is very useful for coarse adjustments of frequency drift over temperature or extending the adjustment ra nge available with the atr register. initial accuracy is best adjusted by enabling the frequency output (using the int register, address 08h), and monitoring the ~irq/f out pin with a calibrated frequency counter. the frequency used is unimportant, although 1hz is the easiest to monitor. the gating time should be set long enough to ensure accuracy to at least 1ppm. the atr should be set to the center position, or 100000bh, to begin with. once the initial measur ement is made, then the atr register can be changed to adjust the frequency. note that increasing the atr register for increased capacitance will lower the frequency, and vice-versa. if the initial measurement shows the frequency is far off, it will be necessary to use the dtr register to do a coarse adjustment. note that most all crystals will have tight enough initial accuracy at room temperature so that a small atr register adjustment should be all that is needed. temperature compensation the atr and dtr controls can be combined to provide crystal drift temperature compensation. the typical 32.768khz crystal has a drift char acteristic that is similar to that shown in figure 17. ther e is a turnover temperature (t 0 ) where the drift is very near zero. the shape is parabolic as it varies with the square of the difference between the actual temperature and t he turnover temperature. if full industrial temperature compensation is desired in an ISL1208 circuit, then both the dtr and atr registers will need to be utilized (total correction range = -94 to +140ppm). table 6. suggested surface mount crystals manufacturer part number citizen cm200s epson mc-405, mc-406 raltron rsm-200s saronix 32s12 ecliptek ecpsm29t-32.768k ecs ecx-306 fox fsm-327 temperature (c) -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 -40-30-20-100 1020304050607080 ppm figure 17. rtc crystal temperature drift ISL1208
18 fn8085.5 august 23, 2006 a system to implement temp erature compensation would consist of the ISL1208, a temperature sensor, and a microcontroller. these devices may already be in the system so the function will just be a matter of implementing software and performing some calculations. fairly accurate temperature compensation can be implemented just by using the crystal manufacture r?s specifications for the turnover temperature t 0 and the drift coefficient ( ). the formula for calculating the oscillator adjustment necessary is: adjustment (ppm) = (t ? t 0 ) 2 * once the temperature curve for a crystal is established, then the designer should decide at what discrete temperatures the compensation will change. since drift is higher at extreme temperatures, the compensation may not be needed until the temperature is greater than 20c from t 0 . a sample curve of the atr sett ing vs. frequency adjustment for the ISL1208 and a typical rtc crystal is given in figure 18. this curve may vary with different crystals, so it is good practice to evaluate a given crystal in an ISL1208 circuit before establishing the adjustment values. this curve is then used to figure what atr and dtr settings are used for compensation. the results would be placed in a lookup table for the microcontroller to access. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operati ng at low frequencies such as 32.768khz are known to pick up noi se very easily if layout precautions are not followed. most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. careful layout of the rtc circuit will avoid noise pickup and insure accurate clocking. figure 19 shows a suggested layout for the ISL1208 device using a surface mount crystal. two main precautions should be followed: do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal . these logic level lines can induce noise in the oscillator circuit to cause misclocking. add a ground trace around the crystal with one end terminated at the chip ground. this will provide termination for emitted noise in the vicinity of the rtc device. in addition, it is a good idea to avoid a ground plane under the x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circuit. if the ~irq/f out pin is used as a clock, it should be routed away from the rtc device as well. the traces for the v bat and v cc pins can be treated as a ground, and should be routed around the crystal. super capacitor backup the ISL1208 device provides a v bat pin which is used for a battery backup input. a super capacitor can be used as an alternative to a battery in cases where shorter backup times are required. since the batt ery backup supply current required by the ISL1208 is extremel y low, it is possible to get months of backup operation using a super capacitor. typical capacitor values are a few f to 1 farad or more depending on the application. if backup is only needed for a few minutes, then a small inexpensive electrolytic capacitor can be used. for extended periods, a low leakage, high capacity super capacitor is the best choice. these devices are available from such vendors as panasonic and murata. the main specifications include working voltage and leakage current. if the application is for charging the capacitor from a +5v 5% supply with a signal diode, then the voltage on the capacitor can vary from ~4.5v to slightly over 5.0v. a capacitor with a rated wv of 5.0v may have a reduced lifetime if th e supply voltage is slightly high. the leakage current should be as small as possible. for example, a super capacitor should be specified with leakage of well below 1a. a standard electrolytic capacitor with dc leakage current in the microamps will have a severely shortened backup time. below are some examples with equations to assist with calculating backup times and required capacitance for the ISL1208 device. the backup supply current plays a major -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 0 5 10 15 20 25 30 35 40 45 50 55 60 atr setting ppm adjustment figure 18. atr setting vs oscillator frequency adjustment figure 19. suggested layout for ISL1208 and crystal ISL1208
19 fn8085.5 august 23, 2006 part in these equations, and a typical value was chosen for example purposes. for a robust design, a margin of 30% should be included to cover supply current and capacitance tolerances over the results of the calculations. even more margin should be included if periods of very warm temperature operat ion are expected. example 1. calculating backup time given voltages and capacitor value in figure 20, use c bat = 0.47f and v cc = 5.0v. with v cc = 5.0v, the voltage at v bat will approach 4.7v as the diode turns off completely. the ISL1208 is specified to operate down to v bat = 1.8v. the capacitance charge/discharge equation is used to estimate the total backup time: rearranging gives c bat is the backup capacitance and dv is the change in voltage from fully charged to loss of operation. note that i tot is the total of the supply current of the ISL1208 (i bat ) plus the leakage current of the capacitor and the diode, i lkg . in these calculations, i lkg is assumed to be extremely small and will be ignored. if an application requires extended operation at temperatures over 50c, these leakages will increase and hence reduce backup time. note that i bat changes with v bat almost linearly (see typical performance curves). this allows us to make an approximation of i bat , using a value midway between the two endpoints. the typical linear equation for i bat vs v bat is: using this equation to solve for the average current given 2 voltage points gives: combining with equation 2 gives the equation for backup time: where c bat = 0.47f v bat2 = 4.7v v bat1 = 1.8v i lkg = 0 (assumed minimal) solving equation 4 for this example, i batavg = 4.387e-7 a t backup = 0.47 * (2.9) / 4.38e-7 = 3.107e6 sec since there are 86,400 seconds in a day, this corresponds to 35.96 days. if the 30% tolerance is included for capacitor and supply current tolerances, then worst case backup time would be: c bat = 0.70 * 35.96 = 25.2 days example 2. calculating a capacitor value for a given backup time referring to figure 20 again, the capacitor value needs to be calculated to give 2 months ( 60 days) of backup time, given v cc = 5.0v. as in example 1, the v bat voltage will vary from 4.7v down to 1.8v. we will need to rearrange equation 2 to solve for capacitance: using the terms described above, this equation becomes: where t backup = 60 days * 86,400 sec/day = 5.18 e6 sec i batavg = 4.387 e-7 a (same as example 1) i lkg = 0 (assumed) v bat2 = 4.7v v bat1 = 1.8v solving gives c bat = 5.18 e6 * (4.387 e-7)/(2.9) = 0.784f if the 30% tolerance is included for tolerances, then worst case cap value would be c bat = 1.3 *.784 = 1.02f figure 20. supercapacitor charging circuit 2.7v to 5.5v v cc v bat gnd 1n4148 c bat i = c bat * dv/dt (eq. 1) dt = c bat * dv/i tot to solve for backup time. (eq. 2) i bat = 1.031e-7*(v bat ) + 1.036e-7 amps (eq. 3) i batavg = 5.155e-8*(v bat2 + v bat1 ) + 1.036e-7 amps (eq. 4) t backup = c bat * (v bat2 - v bat1 ) / (i batavg + i lkg ) (eq. 5) seconds c bat = dt*i/dv (eq. 6) c bat = t backup * (i batavg + i lkg )/(v bat2 ? v bat1 ) (eq. 7) ISL1208
20 fn8085.5 august 23, 2006 ISL1208 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8085.5 august 23, 2006 ISL1208 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994

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